Intel’s options include stopping operating its own NAND foundry and buying in chips, or even sourcing complete SSDs from a third party. Alternatively, it could sell chips to third parties.

Intel need to sale parts to stay afloat, this is why such talks began.

It turns out that the next step to TSMC N7, the company's current-generation 7 nm DUV silicon fabrication node, isn't N7+ (7 nm EUV), but rather it has a nodelet along the way, which the foundry refers to as N7P. This is a generational refinement of N7, but does not use EUV lithography, which means it may not offer the 15-20 percent gains in transistor densities offered by N7+ over N7.

AMD clarified that "7 nm+" in its past presentations did not intend to signify N7+, and that the "+" merely denoted an improvement over N7.

Bad days of TSMC.

AMD also won't use 7nm+ EUV process for Zen 3, as it seems like it is not ready at all

Same is true for their GPUs.

Sad news for TSMC, while marketing "5nm" can work, they can be last process before long pause similar to Intel one.

Early leaks talk about only 3-5% speed improvement assisted with 10-15% price hike.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that its new cutting-edge semiconductor fabrication line in Hwaseong, Korea, has begun mass production.

This is Samsung’s first semiconductor production line dedicated to the extreme ultraviolet (EUV) lithography technology and produces chips using process node of 7 nanometer (nm) and below. The V1 line broke ground in February 2018, and began test wafer production in the second half of 2019. Its first products will be delivered to customers in the first quarter.

The V1 line is currently producing state-of-the-art mobile chips with 7 and 6nm process technology and will continue to adopt finer circuitry up to the 3nm process node.

By the end of 2020, the cumulative total investment in the V1 line will reach USD 6 billion in accordance with Samsung’s plan and the total capacity from 7nm and below process node is expected to triple from that of 2019. Together with the S3 line, the V1 line is expected to play a pivotal role in responding to fast-growing global market demand for single-digit node foundry technologies.

It is all fuzzy with Samsung, as their own chart above shows that they did not have any functioning 7nm line (that also poor Nvidia and other clients figured out hard).

Intel is in talks to sell a unit that makes chips for home internet access gear to MaxLinear Inc.

No final decision has been made and Intel could keep the connected home division,

No, it won't. As Intel is short on money and they need money to stay among leading manufacturers and try to really make mythical 7nm.

We'll see big cuts in all departments this year also, as well as attempts to sell other parts.

TSMC has started reducing its chip capacity support for Huawei, but is still working closely with the China-based vendor in the development for advanced 5nm and 3nm chip solutions.

And this is very dangerous. As can also mean the end of TSMC as leading suplier.

US very much wants Intel to be one, but they are failing.

Intel slashed Xeon prices, and by slashed we mean far more than 50%, but the MSRP didn’t change. Officially there was no change, that pipsqueak AMD has no effect on pricing, carry on folks and look away. Unofficially if you showed your friendly OEM a bid with an AMD CPU there were enough MeetComp dollars flowing to drop prices 2/3rds or more.

Xeon pricing will have huge impact on Intel.

Most probably we'll never see 7nm from them, especially if they will start having issues with notebook CPU prices (and this is second category with huge profits).

Good articles on 7nm AMD chips

AMD has reduced the size of the Core Complex (CCX), a cluster of Zen CPU cores, to about 50% of the 14-nm process generation by moving to the 7-nm process. Compared with the same amount of cache SRAM, the size is about half, and the density of transistors is almost doubled.

The size of CPU cores has also been reduced by half, and as a result, the number of CPU cores installed in the APU (Accelerated Processing Unit) aimed at the main stream has been doubled to eight.

However, this ratio is a bit strange, considering the miniaturization scenario of the conventional CMOS process.

AMD has skipped 10nm, the next process after 14nm, and is moving to a 7nm process. In the process node, the migration is for two generations. This means that the process has been reduced to 50% by miniaturizing the process for two generations. However, with traditional CMOS scaling, if the number of nodes is the same, the CPU core area should be 25%.

The traditional CMOS scaling rule states that a generation of process nodes reduces device area by 50%, thereby doubling transistor density. 4 times for 2 generations. In other words, the area should be 50% at 10nm from the 14nm process and 50% at 10nm to 7nm.

As a result, at 7 nm versus 14 nm, the same core die area is reduced to 25%. According to AMD, this is half the scale of traditional scaling.

• https://pc.watch.impress.co.jp/docs/column/kaigai/1231965.html
• https://pc.watch.impress.co.jp/docs/column/kaigai/1231518.html

L4 cache as dead end

“At some level, another level of cache is inevitable,” says Gianos. “We had a first level of cache and eventually we had a second. And eventually we added a third. And eventually we will have a fourth. It’s more of a question of when and why.

The architects at AMD, who did not want to be directly attributed because in having this conversation they did not want to be misconstrued with AMD promising that it would be adding L4 cache to the Epyc processor line – and to be clear, AMD has said nothing of the kind. But it did recognize that it is the next obvious thing to be thinking about, and just like Intel, believes that every architect is thinking about L4 caches, and it shared some of its thinking on background. Basically, AMD says that the tradeoff in number of cache layers and latency has been well studied in industry and academia, and that with each new cache layer, which is bigger, slower, and more widely accessed, there is a necessary tradeoff that increases the total path out to the DRAM because most designs would not continually speculatively access the cache layers further down in the hierarchy in parallel with cache tag lookup in the upper layers. This is exactly what Intel is also talking about above when Gianos says you need to find a balance between the hit rate and the capacity of the cache – and the L4 is no different.

Big L4 cache is expensive, eats silicon manufacturing capacity and do not bring much of performance increase outside of specific tasks.

https://www.nextplatform.com/2020/01/16/cache-is-king/

Gartner predictions also show that AMD won't continue to add cores and performance so fast.