Intel still has high hopes

GlobalFoundries laying off more than 400 workers at its Fab 8 computer chip factory in Malta last year may have benefited Intel. The staff were laid off after GloFlo decided not to bother with 7nm and to stick with the current cutting-edge 14-nanometre chips, GlobalFoundries was able to reduce its research and development expenses significantly.

Intel is building a $7 billion chip factory known as Fab 42 outside of Chandler, Arizona that is expected to make 7-nanometre chips eventually, and former GlobalFoundries workers that had been part of the 7-nanometre team at Fab 8 would be valuable to Intel as it gets its Fab 42 up and running.

According to LinkedIn dozens of former GlobalFoundries employees have found a home with Intel.

Best Intel hopes now are that to invest funds will want to keep two modern process manufacturers, despite any costs. Otherwise we can see slow Intel demise as 10nm process is clearly total failure for now.

The lead time for production of 7nm chips at Taiwan Semiconductor Manufacturing Company (TSMC) has extended to nearly six months from the previous two months because of strong demand, according to industry sources.

It is not much of demand issue, but issue of still quite low yields. Hence AMD design optimized for large number of defects.

Ryzen 7nm chips can have serious issues with reliability

The original limits for Ryzen 3000 SKUs were:

• 3600 = 4100MHz (80-95°C) / 4200MHz (< 80°C)
• 3600X = 4200MHz (80-95°C) / 4400MHz (< 80°C)
• 3700X = 4200MHz (80-95°C) / 4400MHz (< 80°C)
• 3800X = 4300MHz (80-95°C) / 4550MHz (< 80°C)
• 3900X = 4400MHz (80-95°C) / 4650MHz (< 80°C)

Since then, it appears that the HighTemperature limit has been reduced further to 75°C (from 80°C). New SMUs also have introduced "MiddleTemperature" limit, but that gets disabled when PBO is enabled.

AMD privately discovered fast degradation of CPU dies due to small 7nm process, such fats that it can break within warranty period.

Reliability of Sandy Bridge 32nm CPUs is around 10x-15x more compared to current 7nm process, and it still runs on same or higher clocks. Issue with new process is extreme leaks that can be up to 10x larger than on old processes.

TSMC on Moore Law

First, let's discuss the elephant in the room. Some people believe that Moore's Law is dead because they believe it is no longer possible to continue to shrink the transistor any further. Just to give you an idea of the scale of the modern transistor, the typical gate is about 20 nanometers long. A water molecule is only 2.75 Angstrom or 0.275 nanometer in diameter! You can now start counting the number of atoms in a transistor. At this scale, many factors limit the fabrication of the transistor. The primary challenge is the control of materials at the atomic level. How do you place individual atoms to create a transistor? How do you do this for billions of transistors found on a modern chip? How do you build these chips that have billions of transistors in a cost effective manner?

To address this squarely, TSMC has recently announced our N5P node which further expands our leadership beyond the N5 node that will feature the world’s highest transistor density and offer the fastest performance. After being exposed to our technology roadmap, I can safely state that TSMC has many years of pioneering and innovation ahead of us where we will continue to shrink the individual transistor and continue to improve density. You will hear more from us in the coming months and years as we progress to new nodes.

Beyond the individual transistor, we also need to look at the system level density. Circling back and looking at the classic compute tasks of CPUs and GPUs, the modern chip has extremely fast transistor clock speeds that approach 5 gigahertz and beyond. The central challenge to these compute tasks is actually to keep the CPU and GPU cores fed with data. While this is classically a software challenge, modern architectures and methods for threading have squarely put the performance bottleneck at the hardware level. We have finally seen the limitations of memory caching in the era of big data analytics and AI.

To feed modern fast CPUs, GPUs and dedicated AI Processors, it is critical to provide memory that is both physically closer to the cores that are requesting the data for improved latency, in addition to supplying a higher bandwidth of data for the cores to process. This is what device level density provides. When memory is collocated closer to the logic cores, the system achieves lower latency, lower power consumption and higher overall performance.

Some of you may think that this is a system level concern and not an intrinsic attribute of a device technology. This may be strictly true in the past but the line is already getting blurry between the definition of a chip and the definition of a system. The line will continue to get more blurry and eventually will be completely eliminated. We have now transitioned from an era of design-technology co-optimization (DTCO) to system-technology co-optimization (STCO).

https://www.tsmc.com/english/newsEvents/blog_article_20190814.htm

Ryzen 3xxx supply is really bad now

AMD is saved by preorders and promises, but real supply is quite low and can't keep up with orders.

AMD already postponed announcement 2 times, but due to quite low TSMC yields and due to fact that 7nm lines are fully loaded with Apple and Huawei chips, they can't do better.

Rumors are that up to 30% of AMD chips go to trash bin being fully functional as they can't keep the frequency standards, many works properly only up to 2-2.3Ghz.

Moore’s Law has run out of gas, “and that is profound,” said Victor Peng, CEO of Xilinx.

“You can get one of the three, it’s hard to get two of three, and I would challenge anyone who says they can get three of the three,” he said. Today’s extreme ultraviolet (EUV) lithography systems only remove the complexity of multi-patterning today’s chips, the 7-5-3-nm names of the latest nodes “are all marketing numbers, and no one has fixed the interconnect problem.”

“The cost of designing a 5-nm chip will be astronomical,” limiting the node’s use to a few companies who “can amortize it across multiple designs. Because of the constraints of Moore’s Law, you have to work harder — there’s no freebie in optical scaling anymore.”

3nm marketing nanometers will be tough

This week, at its technology forum ITF USA 2019, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a dual-damascene 21nm pitch test vehicle relevant for manufacturing the 3nm logic technology node. With this test vehicle, a 30 percent improvement in resistance-capacitance product (RC) was obtained compared to previous generations, without impacting reliability. The need for implementing scaling boosters such as self-aligned vias and self-aligned blocks in 3nm and beyond interconnect technologies has been demonstrated.

How it looks in smartphone space

With rising heat dissipation demand from major vendors including Samsung Electronics, LG Electronics, Huawei, Oppo and Xiaomi for their 5G smartphones, half of cooling module shipments for smartphones in the second half of 2019 will be vapor chamber-based solutions, and the other half heatpipe-based ones, according to industry sources.

And it is only small beginning.

Fall of smartphone huge market will be unprecedented and it will destroy some of leading semiconductors manufacturers.

Interesting slides

“It's going to keep going,” said Jim Keller, a semiconductor rock star who joined Intel last year as senior vice president of silicon engineering, and a cohost of the event. “Moore’s law is relentless”

“The working title for this talk was ‘Moore’s law is not dead but if you think so you’re stupid,’" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore’s law. “I’m not pedantic about Moore’s law talking just about transistors shrinking—I’m interested in the technology trends and the physics and metaphysics around that,” Keller says. “Moore’s law is a collective delusion shared by millions of people.”

Keller said Sunday that Intel can sustain that delusion, but that smaller transistors will be just one part of how. On the conventional side, he highlighted Intel’s work on extreme ultraviolet lithography, which can etch smaller features into chips, and smaller transistor designs based on nano-scale wires due to arrive in the 2020s.

Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. “That’s basically already working,” he said.

All this vertical 3D stuff does not work for heavy load chips like CPUs. Only for their SRAM and IO parts may be.

Same as 2011 had been year of 2500K, 2019 is the year of Ryzen 3xxx, and will be next peak before even faster reduction. Industry won't be able to scale further from 16 cores without drastic price increases and thermal output increase.

How slowing down progress look at supercomputers chart