In perspective

Ten little Soldier Boys went out to dine;
One choked his little self and then there were nine.

Nine little Soldier Boys sat up very late;
One overslept himself and then there were eight.

Eight little Soldier Boys travelling in Devon;
One said he'd stay there and then there were seven.

Seven little Soldier Boys chopping up sticks;
One chopped himself in halves and then there were six.

Six little Soldier Boys playing with a hive;
A bumblebee stung one and then there were five.

Five little Soldier Boys going in for law;
One got in Chancery and then there were four.

Four little Soldier Boys going out to sea;
A red herring swallowed one and then there were three.

Three little Soldier Boys walking in the zoo;
A big bear hugged one and then there were two.

Two little Soldier Boys sitting in the sun;
One got frizzled up and then there was one .

One little Soldier Boy left all alone;
He went out and hanged himself and then there were none.

Servers processors plan

Intel expect no progress with 10nm until second half of 2019, at best

10nm Ice Lake based Xeon chips are postponed, They won't appear in 2019 and could be moved as far as 2021-22.

New tech to pack more stuff

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the world-leading research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3. The proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%.

https://www.imec-int.com/en/articles/imec-presents-complementary-fet-cfet-as-scaling-contender-for-nodes-beyond-n3

7nm progress

Taiwan Semiconductor Manufacturing Company (TSMC) has started commercial production of chips built using 7nm process technology.

TSMC will tape out more than 50 chip designs with its 7nm process technology by the end of 2018, Wei said. AI, GPU and cryptocurrency applications take up the majority of the tape-outs, followed by 5G and application processors.

TSMC will also start taping out chips built using an enhanced 7nm node with EUV in the second half of 2018.

5nm plans

TSMC's 5nm node's risk production is scheduled to kick off in the first half of 2019, with mass production at the end of the year or the beginning of 2020,

Details on Intel 10nm

• Logic transistor density of 100.8 mega transistors per mm2, increasing 10nm density 2.7X over the 14nm node
• Utilizes third generation FinFET technology
• Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
• Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

• Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
• First Co metallization and Ru usage in BEOL
• New self-aligned patterning schemes at contact and BEOL

SRAM improvements

Moving contact to reduce footprint

Metallization layers

Micro thinks that EUV not required for DRAM scaling, for now at least

Let's talk about the Company's sort of core leadership in manufacturing technology. I mean obviously Intel was the foundational architect of Moore's Law. The team has had a solid track record of driving performance, combination of you know your leadership in driving Moore's law and silicon process technology as well as architectural innovations as well. And you know just a little bit over a year ago at your Investor Day, the team described Intel being on track to scale logic scale area at a rate of 0.5x every two years, this is from a process technology perspective. Moreover at that event, you discuss Intel having an approximately three-year lead when versus competitors launching equivalent 10 nanometer processes.

Fast forward to today, Intel has delayed the high volume ramp of 10 nanometer, and with the leading foundry guys in the market bringing 7 nanometer products to the market maybe second half of this year arguably with similar sales and area type of benefits, as 10 nanometers, the markets getting a bit concerned that the gap is closing, and this potentially leads to the gap also closing between you and some of your competitors that take advantage of those process technology. So first off, could you just help us understand why Intel has made the decision to delay the 10 nanometer technology?

Murthy Renduchintala

Sure. Well and first of all, I think that silicon leadership is really important in as much as it supports product leadership. Silicon leadership in and of itself is only one of the aspects required. First of all Intel is a product company, it's not necessarily focused on being a merchant foundry. And in addition to silicon leadership, you really also need right architectural capability, the ability to execute silicon programs to predictable timelines, and you need an arsenal of capabilities and packaging, assembly and test technologies. So bringing all of those the weather is really what drives product leadership.

In terms of 10-nanometer, we are shipping 10-nanometer in low volumes. I think that if you go back to when we originally defined the recipe of 10-nanometer back in early 2014, we defined some very aggressive goals for our second-generation hyper-scaling. We targeted a 2.7x scaling factor, from 14-nanometers which was in the very stages of product ramp at that point in time. And 14-nanometers with in and of itself of 2.4x scaling on 22 nanometers, so clearly our engineering team in TMG had very, very ambitious goals in terms of the transistor scaling required.

That required a lot of innovations to come together and maybe those plans were a little bit more aggressive in hindsight than was ideal. And so, therefore we had a little bit of a greater challenge in bringing 10-nanometer to market than we had originally expected. However, the issues that we faced in getting that to prime time yield and not fundamental. We know what to fix and we’re busy going about fixing that. In the meantime, we found tremendous intra-node capability within our 14-nanometer process.

In fact from the very first generation of our 14-nanometer to the latest generation of 14-nanometer product, we've been able to deliver over 70% performance improvement as a result of those intra-node modifications and desirable changes. And that's quite frankly Harlan has given us the ability to make sure that we get 10-nanometer yields right before we go into mainstream production. And so, therefore we’re comfortable with the 14-nanometer roadmap that will give us leadership products in the next 12 to 18 months, as we seek to optimize the cost structure and yields of our 10-nanometer portfolio.

https://seekingalpha.com/article/4174405-intel-intc-presents-jp-morgan-46th-annual-global-technology-media-communications-conference?part=single

No 10nm Intel chips until 2019 on the market

Problems continue.

We continue to make 14 nm process optimizations and architectural innovations in both data center and client products that will be coming this year.
Intel is currently shipping low-volume 10nm product and now expects 10nm volume production to shift to 2019.

https://s21.q4cdn.com/600692695/files/doc_financials/2018/Q1/Q1-2018_EarningsRelease-FINAL.pdf

In is total mess with different tech names

Gwennap writes that the “7-nanometer” technology of TSM and Samsung and Global should be quite close to Intel’s 10-nanometer process, with the result that "the three leading foundries, which serve all of Intel’s major competitors, [will be] on the same level as the x86 giant."

Taiwan Semi’s 7-nano technology “appears similar to Intel’s 10nm, within a fraction of a node,” he writes. It’s even possible the three competitors will leap-frog Intel’s results before the chip giant can move to its next technology, sometime in 2021, writes Gwennap.

Very interesting information

Engineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure that they will be able to squeeze commercial advantages from them even at 5 nm.

Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10–25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20–30% at 7 nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.

“Area still scales in strong double digits, but the hidden cost increases in masks means the actual cost advantages and other improvements are starting to slow down … It’s not clear what will remain at 5 nm,” said Penzes, suggesting that 5-nm nodes may only be extensions of 7 nm.

Versions of today’s FinFET transistors will be used down to the 5-nm node, said technologists from Synopsys and Samsung on the panel. Below a width of about 3.5 nm, FinFETs will hit a hard limit. Samsung has announced plans to use a gate-all-around transistor for a 4-nm process that it aims to have in production by 2020.

https://www.eetimes.com/document.asp?doc_id=1333109&page_number=1