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Semicinductors industry has serious issues, stop will follow
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    After more than 50 years of miniaturization, the transistor could stop shrinking in just five years, this is the prediction of the 2015 International Technology Roadmap for Semiconductors, which was officially released earlier this month.

    After 2021 it will no longer be economically desirable for companies to continue to shrink the dimensions of transistors in microprocessors. Instead, chip manufacturers will turn to other means of boosting density, namely turning the transistor from a horizontal to a vertical geometry and building multiple layers of circuitry, one on top of another.

    19 companies were developing and manufacturing logic chips with leading-edge transistors in 2001. Today, there are just four: Intel, TSMC, Samsung, and GlobalFoundries.

    http://spectrum.ieee.org/tech-talk/computing/hardware/transistors-will-stop-shrinking-in-2021-moores-law-roadmap-predicts

    This guys did not tell you full truth. For all last manufacturer processes companies had marketing process values and real process values. In old good times each generation of process really meant proportional reduction of all elements, it is no longer the case. Especially with 14nm processes that are not really 14nm.

    Optimistic statements with many 3D wafers and such are overly optimistic. Due to difficulties such process is very costly and available to top manufacturers only. All such processes are not usable in high speed and thermally intense areas due to cooling issues, this mean GPUs and CPUs. Now it is only some flash memory that is made using similar approach.

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  • 98 Replies sorted by
  • Intel 3D stacking tech, nothing new

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    Note that it is badly suited for high performance chips due to cooling problems.

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  • New Intel Core Roadmap

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  • More optimism before collapse into the wall

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  • 3nm aka the wall aka final stop

    Dr. Jung also introduced some of recent research and development in future silicon technology, including MRAM, a non-volatile memory solution embedded in conventional logic process, and 3nm Gate-All-Around (GAA) technology.

    MRAM is one of the examples of new semiconductor devices that consume much less power. As memory density becomes higher, MRAM’s power efficiency becomes more prominent, consuming only 0.5% of power compared to SRAM at 1,024Mb. MRAM also has smaller cell area, which allows design flexibility.

    Samsung’s unique GAA technology called Multi-Bridge-Channel FET(MBCFET) uses vertically stacked multiple nanosheet channels. With variable width of nanosheet, this technology provides not only optimal performance and power characteristics, but also high design flexibility. Furthermore, MBCFET is fabricated using 90% or more of FinFET process with only a few revised masks, allowing easy migration.

    With one of its newly published papers at 2018 IEDM, Samsung Electronics shared the development progress of 3nm, a successful demonstration of fully functioning high-density SRAM circuit. The development of Samsung’s first process node applying MBCFET technology is on schedule.

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    Intel try to mitigate 10nm cancelling rumors. But already transfer some manufacturing areas back to 14nm.

    Intel has no even definite plans for 7nm as had been told.

    Main idea is same as for camera manufacturers - company just hiked prices.

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  • Just wow!

    SemiAccurate has learned that Intel just pulled the plug on their struggling 10nm process. Before you jump to conclusions, we think this is both the right thing to do and a good thing for the company.

    For several years now SemiAccurate has been saying the the 10nm process as proposed by Intel would never be financially viable. Now we are hearing from trusted moles that the process is indeed dead and that is a good thing for Intel, if they had continued along their current path the disaster would have been untenable. Our moles are saying the deed has finally been done.

    Intel managers decline this

    Media reports published today that Intel is ending work on the 10nm process are untrue. We are making good progress on 10nm. Yields are improving consistent with the timeline we shared during our last earnings report.

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    Intel own documents changes.

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  • Industry rumors are that Intel 10nm won't be usable for any 4 core or better CPUs for at least 2020.

    Company has extreme problems with 10nm that they can't solve for many years.

  • In fact, 3nm and beyond may never happen at all, as there are a multitude of unknowns and challenges in the arena. Perhaps chip scaling will finally run out of steam by then.

    At each node, process cost and complexity are skyrocketing, so now the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer. In addition, fewer foundry customers can afford to move to advanced nodes.

    One of the reasons here - capitalism, as everything is made under NDAs, buying and going around lot of patents. The more complex thing become - the more capitalism and it's son - copyright are holding progress.

    https://semiengineering.com/transistor-options-beyond-3nm/

  • According to our sources, ATIC (Which owns about nine-tens of Globalfoundries) is in the process of looking for potential buyers for GlobalFoundries.

    Nice.

    So from 4 remaining competitors:

    • GlobalFoundries cancelled new technology, out of competition and will do 14nm and less only
    • Intel has huge issues with 10nm (it is actually same or even better than others 7nm)
    • TSMC use huge Apple money and seems to be on track for 7nm (yet not fully true 7nm)
    • Samsung is similar to TSMC, but can also use their own big smartphones profits
  • In perspective

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    Ten little nigger boys went out to dine One choked his little self, and then there were nine.

    Nine little nigger boys sat up very late One overslept himself, and then there were eight.

    Eight little nigger boys traveling in Devon One said he'd stay there, and then there were seven.

    Seven little nigger boys chopping up sticks One chopped himself in half, and then there were six.

    Six little nigger boys playing with a hive A bumble-bee stung one, and then there were five.

    Five little nigger boys going in for law One got in chancery, and then there were four.

    Four little nigger boys going out to sea A red herring swallowed one, and then there were three.

    Three little nigger boys walking in the zoo A big bear hugged one, and then there were two.

    Two little nigger boys sitting in the sun One got frizzled up, and then there was one.

    One little nigger boys living all alone He went and hanged himself and then there were none.

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  • At 7mm we lost another player - GLOBALFOUNDRIES

    GF is realigning its leading-edge FinFET roadmap to serve the next wave of clients that will adopt the technology in the coming years. The company will shift development resources to make its 14/12nm FinFET platform more relevant to these clients, delivering a range of innovative IP and features including RF, embedded memory, low power and more. To support this transition, GF is putting its 7nm FinFET program on hold indefinitely and restructuring its research and development teams to support its enhanced portfolio initiatives. This will require a workforce reduction, however a significant number of top technologists will be redeployed on 14/12nm FinFET derivatives and other differentiated offerings.

    https://globenewswire.com/news-release/2018/08/27/1557178/0/en/GLOBALFOUNDRIES-Reshapes-Technology-Portfolio-to-Intensify-Focus-on-Growing-Demand-for-Differentiated-Offerings.html

  • Servers processors plan

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  • Stop already happened for Intel and it'll go back

    What Intel is not telling you, or the analysts, is that the 10nm you may get in late 2019 is not the 10nm they had intended to come out in 2015. More importantly this new process is a significant step backward from the 10nm they promised, as touted in their manufacturing day. How much of a step backwards? Several of SemiAccurate’s moles are saying it is effectively a 12nm process rather than a 10nm process, and the technical changes more than back that claim up.

    https://semiaccurate.com/2018/08/02/intel-guts-10nm-to-get-it-out-the-door/

  • Intel expect no progress with 10nm until second half of 2019, at best

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  • 10nm Ice Lake based Xeon chips are postponed, They won't appear in 2019 and could be moved as far as 2021-22.

  • Problems now affect notebook vendors

    Global notebook vendors including HP, Dell, Lenovo, Acer and Asustek Computer will be unable to launch new models fitted with Intel's new-generation CPUs in the second half of 2018 as scheduled, as the release of Intel's new offerings will not come soon enough for this year's high season

  • New tech to pack more stuff

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    At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the world-leading research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3. The proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%.

    https://www.imec-int.com/en/articles/imec-presents-complementary-fet-cfet-as-scaling-contender-for-nodes-beyond-n3

  • 7nm progress

    Taiwan Semiconductor Manufacturing Company (TSMC) has started commercial production of chips built using 7nm process technology.

    TSMC will tape out more than 50 chip designs with its 7nm process technology by the end of 2018, Wei said. AI, GPU and cryptocurrency applications take up the majority of the tape-outs, followed by 5G and application processors.

    TSMC will also start taping out chips built using an enhanced 7nm node with EUV in the second half of 2018.

    5nm plans

    TSMC's 5nm node's risk production is scheduled to kick off in the first half of 2019, with mass production at the end of the year or the beginning of 2020,

  • Details on Intel 10nm

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    • Logic transistor density of 100.8 mega transistors per mm2, increasing 10nm density 2.7X over the 14nm node
    • Utilizes third generation FinFET technology
    • Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
    • Minimum metal pitch shrinks from 52 nm to 36 nm

    Process Highlights:

    • Deepest scaled pitches of current 10 nm and upcoming 7 nm technologies
    • First Co metallization and Ru usage in BEOL
    • New self-aligned patterning schemes at contact and BEOL

    SRAM improvements

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    Moving contact to reduce footprint

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    Metallization layers

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