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Semicinductors industry has serious issues, stop will follow
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    After more than 50 years of miniaturization, the transistor could stop shrinking in just five years, this is the prediction of the 2015 International Technology Roadmap for Semiconductors, which was officially released earlier this month.

    After 2021 it will no longer be economically desirable for companies to continue to shrink the dimensions of transistors in microprocessors. Instead, chip manufacturers will turn to other means of boosting density, namely turning the transistor from a horizontal to a vertical geometry and building multiple layers of circuitry, one on top of another.

    19 companies were developing and manufacturing logic chips with leading-edge transistors in 2001. Today, there are just four: Intel, TSMC, Samsung, and GlobalFoundries.

    http://spectrum.ieee.org/tech-talk/computing/hardware/transistors-will-stop-shrinking-in-2021-moores-law-roadmap-predicts

    This guys did not tell you full truth. For all last manufacturer processes companies had marketing process values and real process values. In old good times each generation of process really meant proportional reduction of all elements, it is no longer the case. Especially with 14nm processes that are not really 14nm.

    Optimistic statements with many 3D wafers and such are overly optimistic. Due to difficulties such process is very costly and available to top manufacturers only. All such processes are not usable in high speed and thermally intense areas due to cooling issues, this mean GPUs and CPUs. Now it is only some flash memory that is made using similar approach.

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  • 67 Replies sorted by
  • James Prior from AMD - progress in CPU frequencies ended

  • In is total mess with different tech names

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    Gwennap writes that the “7-nanometer” technology of TSM and Samsung and Global should be quite close to Intel’s 10-nanometer process, with the result that "the three leading foundries, which serve all of Intel’s major competitors, [will be] on the same level as the x86 giant."

    Taiwan Semi’s 7-nano technology “appears similar to Intel’s 10nm, within a fraction of a node,” he writes. It’s even possible the three competitors will leap-frog Intel’s results before the chip giant can move to its next technology, sometime in 2021, writes Gwennap.

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  • Nvidia rising development costs

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    yet they have lot of margin left

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  • Very interesting information

    Engineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure that they will be able to squeeze commercial advantages from them even at 5 nm.

    Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10–25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20–30% at 7 nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.

    “Area still scales in strong double digits, but the hidden cost increases in masks means the actual cost advantages and other improvements are starting to slow down … It’s not clear what will remain at 5 nm,” said Penzes, suggesting that 5-nm nodes may only be extensions of 7 nm.

    Versions of today’s FinFET transistors will be used down to the 5-nm node, said technologists from Synopsys and Samsung on the panel. Below a width of about 3.5 nm, FinFETs will hit a hard limit. Samsung has announced plans to use a gate-all-around transistor for a 4-nm process that it aims to have in production by 2020.

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    https://www.eetimes.com/document.asp?doc_id=1333109&page_number=1

  • Spending in 2017

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  • 5nm issues

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    Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5-nm nodes. They are applying an array of techniques to eliminate them but, so far, see no clear solution.

    A retired Intel lithographer predicted that engineers will be able to create 5-nm and even 3-nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.

    By 2024, defects could become so widespread that conventional processors will not be able to be made in leading-edge processes, said Borodovsky.

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  • UMC start cutting expenses for advanced processes (14nm an up).

    Total capital expenses are also falling. In 2016 it was $2 billions, in 2017 it was only $1.44 billions and in 2018 it is planned to be only 1.1 billions

    As predicted - each new step will require reduction in number of companies.

  • Interesting comparison of processes (it is prognosis for 2020 year processes)

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    https://www.eetimes.com/document.asp?doc_id=1332860

  • Some old but useful slide from Intel

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  • At CES 2018 Gregory Bryant told that high volume 10nm processor delivery to companies will start only in second half of 2018, may be closer to the end of year.

  • Intel issues are so serious that only 10nm CPUs they managed to make in 2017 are 2.2Ghz (in Turbo, normal is lower) 2 core one, without build in GPX. This allowed to make chip very small, so with horrible yields some can still work.

  • Serious issues with Intel 10nm process

    To say yields were bad was understating things to a degree that even the classic British humorists would not dare to delve. Normally from tapeout to product on the shelves, Intel takes ~12 months for server SKUs, less for consumer. According to SemiAccurate moles, it has been ~16 months and counting.

    Intel is insistent nothing is wrong but if you look at their recent Manufacturing Day messaging, one thing stood out. That thing is 20+ years of stating process progress was overturned with a new way of measuring progress that said that the 2+ year slip, at that time, for the 10nm process was not actually a problem, it was a technological breakthrough instead.

    If you look at Intel roadmaps, the cadence should have gone 32nm (Westmere/Arrandale) in 2010, Sandy Bridge in 2011, Ivy Brige in 2012, Haswell in 2013, Broadwell in 2014, Sky Lake in 2015, Cannon Lake (10nm) in January 2016, Icelake (10nm) in January of 2017, and Tigerlake/Firelake (7nm) at CES in about 2 weeks aka January 2018. Instead there were the slips described above and Cannon, due ~2 years ago, isn’t out. Instead we have multiple “new architectures” that seem to pop up on the Intel roadmaps as soon as OEMs need to start production on the 10nm parts that were previously there.

    10nm is now set for late 2018, officially, and that is where things really begin.

    https://semiaccurate.com/2017/12/20/state-intels-10nm-process/

  • Many believe that the industry has slipped behind the pace of innovation prescribed by Moore's Law, which states the number of transistors per square inch of a chip would double every 18 months. Today, according to Su, it takes about 2.4 years to double the density of transistors per square inch. In addition, increasing die sizes are becoming economically problematic, memory bandwidth has become less efficient over time and the power consumption of SoCs is increasing by about 7 percent per year.

    https://www.eetimes.com/document.asp?doc_id=1332706

  • Intel will use cobalt in on the bottom two layers of its 10-nm interconnect to get a five- to ten-fold improvement in electromigration and a two-fold reduction in via resistance. It represents the first time that a chip maker has detailed plans to introduce cobalt — a brittle metal long considered a promising dielectric candidate — in a process, according to G. Dan Hutcheson.

    Globalfoundries, which has said previously that it would insert EUV at the 7-nm node, detailed a platform that is entirely based on immersion optical lithography but is designed to enable the insertion of EUV for specific levels to improve cycle time and manufacturing efficiency. Gary Patton, Globalfoundries chief technology officer and senior vice president of global R&D, said in an interview with EE Times that kinks in EUV still need to be worked out — chiefly pellicle and inspection technologies — but that Globalfoundries is currently installing its first EUV production tools at its Fab 8 in upstate New York.

    https://www.eetimes.com/document.asp?doc_id=1332696

  • 7nm is badly required for memory also

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    AMD forgot to add that most progress is due to more cores :-)

    And here it is

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    AMD also said that they expect same size 7nm die CPU and GPUs to be twice more expensive.

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  • As it is too soon for 8nm, second gen 10nm is presented

    Samsung announced that its Foundry Business has commenced mass production of System-on-Chip (SoC) products built on its second generation 10-nanometer (nm) FinFET process technology, 10LPP (Low Power Plus).

    10LPP process technology allows up to 10-percent higher performance or 15-percent lower power consumption compared to its first generation 10nm process technology, 10LPE (Low Power Early). As this process is derived from the already proven 10LPE technology, it offers competitive advantages by greatly reducing turn-around time from development to mass production and by providing significantly higher initial manufacturing yield.

  • Samsung Electronics secured new customers from the U.S. and China for its 7-nano foundry business. This indicates that it succeeded in making a counterattack after it lost rights to produce Qualcomm’s 7-nano chips to TSMC. It is heard that it is finalizing a negotiation with Hwasung-si regarding construction of new 7-nano plant and finalize administrative procedures early December at the earliest. Positive forecast is seen for its 7-nano foundry business.

    Qualcomm and Broadcom are designing next-generation chips through TSMC’s7-nano PDK. TSMC is planning to produce 7-nano chips by using normal steppers repeatedly. Due to this reason, many customers including Qualcomm decided to mass-produce their first 7-nano chips through TSMC.

    It is expected that Samsung Electronics will be slightly late in commercializing 7-nano process than TSMC. However it has been emphasizing that its 7-nano process that is applied with EUV (Extreme Ultraviolet) photolithography technology is truly the next-generation process from all aspects such as area, performance, and amount of electricity consumption.

    So, finally they are forced to do EUV.

  • Poor Moore law, they constantly want to dig up the grave and get out the corpse

    The Moore's Law that sets the pace of the semiconductor development can last two more generations, as the process technology may hit bottlenecks after advancing to 3nm node from the existing 7nm and future 5nm nodes, Tsai Ming-kai, chairman of Taiwan's leading IC designer MediaTek, has said.

  • Intel 10nm state

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  • More surprises

    Moore's Law has become invalid for a while, as the time needed for the transistor density to double is no longer 18-24 months, Morris Chang, chairman of Taiwan Semiconductor Manufacturing Company (TSMC) said.

    TSMC will continue to increase transistor densities in the coming eight years, but will see a major challenge in 2025.

    ASML CEO Peter Wennick said at the same forum that his company has worked out its technology development plans through 2030. It might be technologically feasible for ASML to carry out the plans, but the economic feasibility of the plans would meet with challenges before 2030.

  • Intel and Globalfoundries will describe their 10nm and 7nm process nodes, respectively at the International Electron Devices Meeting (IEDM) in December. The event also will host papers pointing to new directions in memories, medical and flexible electronics and transistors beyond today’s FinFETs.

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    Intel will discuss several aspects of its 10nm node first unveiled in March. It sports FinFETs with a 7nm fin width at a 34nm pitch and a 46nm fin height made using self-aligned quadruple patterning. A 204 Mbit SRAM made in the process packs separate high-density, low voltage and high-performance cells that measure from 0.0312µm2 to 0.0441µm2.

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  • Samsung Electronics 8nm FinFET process

    Samsung's new 8LPP process provides up to 10% lower power consumption with up to 10% area reduction from 10LPP through narrower metal pitch. 8LPP will provide differentiated benefits for applications including mobile, cryptocurrency and network/server, and is expected to be applied to many other high-performance applications, the company said.

    "8LPP will have a fast ramp since it uses proven 10nm process technology while providing better performance and scalability than current 10nm-based products."

  • Intel afraid of EUV

    A race is on to qualify advanced semiconductor process technologies using extreme ultraviolet (EUV) lithography, but Intel is said to be sitting on the sidelines.

    Samsung and TSMC are racing to announce some level of manufacturing with EUV next year. But Intel is said not to be ordering materials needed for EUV at the same rate, according to one source that asked not to be named.